By Swarup Bhunia, Saibal Mukhopadhyay
Layout issues for low-power operations and robustness with appreciate to adaptations in general impose contradictory standards. Low-power layout ideas akin to voltage scaling, dual-threshold task and gate sizing may have huge destructive impression on parametric yield less than method diversifications. This e-book specializes in circuit/architectural layout recommendations for reaching low strength operation below parameter adaptations. We think of either common sense and reminiscence layout points and canopy modeling and research, in addition to layout method to accomplish at the same time low energy and version tolerance, whereas minimizing layout overhead. This e-book will talk about present commercial practices and rising demanding situations at destiny expertise nodes.
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Extra info for Low-Power Variation-Tolerant Design in Nanometer Silicon
19 (a) An SRAM cell with breakdown in left pull-down FET simulated by connecting a resistor. (b) Change in Vmin with resistance. Igate threshold represents the maximum gate leakage this cell can tolerate before suddent jump in Vmin during breakdown. For example, Fig. 19 shows the simulation of gate–dielectric breakdown in the left pull-down FET of an SRAM cell by connecting a resistor between the gate and source. The value of resistance is varied to obtain the change in minimum operating voltage (Vmin ).
Weaker pull-down NFET will also reduce the read current resulting in increased access time. Read current dictates how fast the BL discharges through the series combination of AXL and NL (for VL = “0”). Since reading is getting unstable due to static stress, writing will become easier. For example, flipping the left node from “0” to “1” will become easier because NL has become weak whereas PL retains its original strength. Also flipping the right node from VDD NBTI VDD AXL PL PR VL VR NL + Vt BR BL BR BL PL +| Vt| AXL AXR PR VL VR NL NR AXR NR WL WL (a) (b) Fig.
Bhushan M, Ketchen M, Polonsky S, Gattiker A, (2006) Ring oscillator based technique for measuring variability statistics. In: International conference on microelectronics text structure, 87–92 60. Karl E, Singh P, Blaauw D, Sylvester D (2008) Compact In-Situ sensors for monitoring negative bias temperature instability effect and oxide degradation. In: International conference on solid state circuits, 410–413 61. Keane J, Wang V, Persaud D, Kim C (2010) An all-In-One silicon odometer for separately monitoring HCI, BTI and TDDB.