ACM transactions on design automation of electronic systems by M. R. Greenstreet on formal verification, K-J Le, J. J.

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By M. R. Greenstreet on formal verification, K-J Le, J. J. Tang, T. C. Huang on BIFEST, V. S. S. Nair on spectral based heuristics, others C. Kern

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Extra resources for ACM transactions on design automation of electronic systems (April)

Example text

Reducing the power dissipation requires an in-depth examination of each system component, and research over the past few years has been very active in this area [Brooks et al. 2000; Vijaykrishnan et al. 2000]. Power is consumed whenever computing elements are accessed/activated (called dynamic power), and even when the elements are idle (called leakage power). While the latter becomes particularly important with billions of transistors clocked at high frequencies expected to be packed on a single chip, today’s main concern is still the dynamic power, which is proportional to the number of times that the device is exercised.

After obtaining the clocking scheme as outlined in the previous section, we can always eliminate the clock connected to the gates in the CFI of the primary outputs. As Figure 15 shows, the clock connected to gate 7 in Figure 2 can be deleted without affecting the correct operation of the circuit. After removing the clock, if gates 7, 8, and 9 finally keep the precharge value, they still have the entire duration of the evaluation period to perform the precharge properly. Otherwise, they would still evaluate correctly.

In contrast, our approach can still work with a reasonably sized iTLB, and can generate the addresses directly in several situations without requiring comparisons, and without incurring any performance penalties. We also show in this article how this approach can be better than a multilevel iTLB from both power and performance angles. The remainder of this article is organized as follows: Background on cache and iTLB lookup mechanisms is presented in Section 2. The details of our approach are given in Section 3.

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